This invention relates to a method of fabricating semiconductor integrated circuits, more particularly to a method of forming bipolar semiconductor integrated circuits in which the emitter region is self-aligned with the base region.
A prior example of this type of fabrication method is disclosed in Japanese Patent Application No. 1986/131698, and will be described with reference to the sectional process diagrams in FIG. 1A through FIG. 1G.
First, as shown in FIG. 1A, known techniques are used to form an N.sup.+ -type buried collector layer 2, an N.sup.- -type epitaxial layer 3, an isolation region 4, and a collector sink layer 5 on a P.sup.- -type silicon substrate 1; then a polysilicon film 7 and an oxidation-resistant film 8 are deposited, in this sequence.
Next, as shown in FIG. 1B, photo-etching is used to form photo-resist patterns 80.sub.1 to 80.sub.3 and oxidation-resistant patterns 8.sub.1 to 8.sub.3 ; these patterns are used as masks for boron ion implantation into the polysilicon film 7; then after the photoresist 80 is removed, a heavily-doped base layer 6.sub.2 is created by heat treatment.
Then, as shown in FIG. 1C, the polysilicon film 7 is selectively oxidized so that the polysilicon films 7.sub.1, 7.sub.2, and 7.sub.3 that will become the electrodes of the transistor are individually separated by a silicon oxide film 9.
Next, as shown in FIG. 1D, the oxidation-resistant patterns 8.sub.1 to 8.sub.3 are removed, and after the surfaces of the polysilicon films 7.sub.1, 7.sub.2, and 7.sub.3 have been thinly oxidized, boron is introduced through the afore-mentioned oxide film into the polysilicon 7.sub.1, using photoresists 80.sub.5 and 80.sub.6 patterned by photo-etching as a mask; then after the resists 80.sub.5 and 80.sub.6 have been removed, boron ions are implanted over the entire surface.
Then, as shown in FIG. 1E, heat treatment is carried out in a non-oxidizing atmosphere to diffuse the boron out of the polysilicon 7.sub.1 and 7.sub.2 and form a passive base layer 10 and an active base layer 6.sub.1, after which contact holes 12.sub.1 to 12.sub.3 are opened.
Next, as shown in FIG. 1F, the polysilicon surface in the contact hole areas is thinly oxidized using photoresists 80.sub.9 to 80.sub.11 that have been patterned by photo-etching as a mask, arsenic ions are implanted into the polysilicon films 7.sub.2 and 7.sub.3 over the emitter region and over the collector electrode contact.
Then, as shown in FIG. 1G, after the photoresists 80.sub.9 to 80.sub.11 have been removed, heat treatment is carried out in a non-oxidizing atmosphere to form an emitter layer 11 in the active base layer 6.sub.1.
In this prior-art fabrication method, however, in order to self-align the emitter region and the active base region, the chip is structured so that the active base region is surrounded by a thick silicon oxide film. A heavily-doped base layer is therefore needed to make electrical contact between the active base layer and the passive base layer that interfaces with the base electrode, and the resistance of this base must be reduced in order to improve the switching speed of the transistor. It is therefore necessary to reduce the resistance of the heavily-doped base layer by raising the dopant concentration in the heavily-doped base layer. An extremely high dopant concentration in the heavily-doped base layer creates the following difficulties, thus limiting the attainable switching speed of the transistor.
(A) The heavily-doped base layer is widened by the heat treatment (selective oxidation, active base layer formation, and emitter layer formation) after forming the heavily-doped base layer. This has the following effects (A-1) to A-3): PA0 (B) The junction of the heavily-doped base layer is deepened by the heat treatment (selective oxidation, active base layer formation, emitter layer formation) after the formation of the heavily-doped base layer. Accordingly, if the thickness of the epitaxial layer is reduced to reduce the collector resistance and improve the switching speed of the transistor, the collector-base breakdown voltage is reduced. PA0 (a) forming a first film (105) on the surface of a region which is to become an active region on a semiconductor substrate having a first type of conductivity; PA0 (b) implanting a first dopant through the first film (105) to impart the first type of conductivity to the surface region of the active region; PA0 (c) forming a second film (107) on the surfaces of the active region; PA0 (d) selectively removing part (108) of the second film (107) and the first film (105) on a region which is to become a base electrode region (119); PA0 (e) forming a third film (109) on the surface of the active region to form a concavity at the base electrode region and convexes at regions which are to become emitter and active base regions (118, 110); PA0 (f) implanting a second dopant into the third film (109); PA0 (g) diffusing the second dopant from the third film (109) into part or all of the active region; PA0 (h) forming a fourth film (112) by an RF-bias sputtering in the concavity formed in the preceding step (e) and the central part of the convexity formed in the preceding step (e), the central part of the convexity being positioned directly over the emitter region (118); PA0 (i) removing the fourth film (112) formed in regions outside the active region to leave the fourth film (112) over the emitter region (118), the base electrode region (119) and the collector electrode contact region (121); PA0 (j) selectively removing those parts of the third film (109) that are not covered by the fourth film (112) and are disposed above the surface of the second film (107); PA0 (k) removing the fourth film (112) to leave convexes (109-1, 109-2) over the emitter region (118) and at the collector electrode contact region (121) and a concavity between these convexes; PA0 (l) forming a fifth film (114) by an RF-bias sputtering in the concavity left by the preceding step (k) such that the surface of the third film (109) is exposed; PA0 (m) selectively removing the part of the third film (109) not covered by the fifth film (114), the parts of the second film (107), and the first film (105) under the part of the third film (109) to form windows (115, 116) exposing the emitter region (118) and the collector electrode contact region (112); PA0 (n) forming a sixth film (117) on the surface of the active region; PA0 (o) doping a third dopant into the sixth film (117), the third dopant forming a second type of conductivity; PA0 (p) selectively removing that portion of the sixth film (117) disposed above the surface of the second film (107); and PA0 (q) diffusing the third dopant from the sixth film (117) into part or all of the active region to impart the second type of conductivity to the active region.
(A=1) The area that faces the buried collector layer is increased, thus increasing the base-collector capacitance. It thus limits the switching speed of the transistor. PA1 (A-2) The heavily-doped base layer is brought into contact with the emitter layer, increasing the base-emitter junction capacitance. It thus limits the switching speed of the transistor. PA1 (A-3) The area of the active base layer is reduced, degrading the current gain of the transistor.